Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* usb-omap.h - Platform data for the various OMAP USB IPs
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com
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*/
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#define OMAP3_HS_USB_PORTS 3
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enum usbhs_omap_port_mode {
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OMAP_USBHS_PORT_MODE_UNUSED,
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OMAP_EHCI_PORT_MODE_PHY,
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OMAP_EHCI_PORT_MODE_TLL,
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OMAP_EHCI_PORT_MODE_HSIC,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
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};
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struct usbtll_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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};
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struct ehci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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unsigned phy_reset:1;
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};
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struct ohci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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unsigned es2_compatibility:1;
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};
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struct usbhs_omap_platform_data {
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int nports;
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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struct ehci_hcd_omap_platform_data *ehci_data;
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struct ohci_hcd_omap_platform_data *ohci_data;
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/* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
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unsigned single_ulpi_bypass:1;
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unsigned es2_compatibility:1;
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unsigned phy_reset:1;
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};
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/*-------------------------------------------------------------------------*/
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struct omap_musb_board_data {
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u8 interface_type;
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u8 mode;
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u16 power;
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unsigned extvbus:1;
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void (*set_phy_power)(u8 on);
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void (*clear_irq)(void);
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void (*set_mode)(u8 mode);
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void (*reset)(void);
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};
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enum musb_interface {
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MUSB_INTERFACE_ULPI,
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MUSB_INTERFACE_UTMI
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};
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