Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
73 lines
1.3 KiB
YAML
73 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence TTC - Triple Timer Counter
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maintainers:
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- Michal Simek <michal.simek@amd.com>
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properties:
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compatible:
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const: cdns,ttc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 3
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description: |
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A list of 3 interrupts; one per timer channel.
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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timer-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Bit width of the timer, necessary if not 16.
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"#pwm-cells":
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const: 3
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required:
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- compatible
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- reg
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- clocks
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allOf:
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- if:
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not:
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required:
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- "#pwm-cells"
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then:
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required:
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- interrupts
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additionalProperties: false
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examples:
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- |
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ttc0: ttc0@f8001000 {
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interrupt-parent = <&intc>;
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interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
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compatible = "cdns,ttc";
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reg = <0xF8001000 0x1000>;
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clocks = <&cpu_clk 3>;
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timer-width = <32>;
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};
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- |
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pwm: pwm@f8002000 {
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compatible = "cdns,ttc";
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reg = <0xf8002000 0x1000>;
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clocks = <&cpu_clk 3>;
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timer-width = <32>;
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#pwm-cells = <3>;
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};
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