Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2025 ROHM Semiconductors
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*
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* The digital interface of trhe BD96802 PMIC is a reduced version of the
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* BD96801. Hence the BD96801 definitions are used for registers and masks
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* while this header only holds the IRQ definitions - mainly to avoid gaps in
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* IRQ numbers caused by the lack of some BUCKs / LDOs and their respective
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* IRQs.
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*/
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#ifndef __LINUX_MFD_BD96802_H__
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#define __LINUX_MFD_BD96802_H__
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/* ERRB IRQs */
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enum {
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/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
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BD96802_OTP_ERR_STAT,
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BD96802_DBIST_ERR_STAT,
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BD96802_EEP_ERR_STAT,
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BD96802_ABIST_ERR_STAT,
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BD96802_PRSTB_ERR_STAT,
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BD96802_DRMOS1_ERR_STAT,
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BD96802_DRMOS2_ERR_STAT,
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BD96802_SLAVE_ERR_STAT,
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BD96802_VREF_ERR_STAT,
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BD96802_TSD_ERR_STAT,
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BD96802_UVLO_ERR_STAT,
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BD96802_OVLO_ERR_STAT,
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BD96802_OSC_ERR_STAT,
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BD96802_PON_ERR_STAT,
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BD96802_POFF_ERR_STAT,
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BD96802_CMD_SHDN_ERR_STAT,
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BD96802_INT_SHDN_ERR_STAT,
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/* Reg 0x55 BUCK1 ERR IRQs */
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BD96802_BUCK1_PVIN_ERR_STAT,
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BD96802_BUCK1_OVP_ERR_STAT,
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BD96802_BUCK1_UVP_ERR_STAT,
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BD96802_BUCK1_SHDN_ERR_STAT,
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/* Reg 0x56 BUCK2 ERR IRQs */
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BD96802_BUCK2_PVIN_ERR_STAT,
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BD96802_BUCK2_OVP_ERR_STAT,
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BD96802_BUCK2_UVP_ERR_STAT,
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BD96802_BUCK2_SHDN_ERR_STAT,
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};
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/* INTB IRQs */
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enum {
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/* Reg 0x5c (System INTB) */
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BD96802_TW_STAT,
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BD96802_WDT_ERR_STAT,
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BD96802_I2C_ERR_STAT,
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BD96802_CHIP_IF_ERR_STAT,
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/* Reg 0x5d (BUCK1 INTB) */
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BD96802_BUCK1_OCPH_STAT,
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BD96802_BUCK1_OCPL_STAT,
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BD96802_BUCK1_OCPN_STAT,
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BD96802_BUCK1_OVD_STAT,
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BD96802_BUCK1_UVD_STAT,
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BD96802_BUCK1_TW_CH_STAT,
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/* Reg 0x5e (BUCK2 INTB) */
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BD96802_BUCK2_OCPH_STAT,
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BD96802_BUCK2_OCPL_STAT,
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BD96802_BUCK2_OCPN_STAT,
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BD96802_BUCK2_OVD_STAT,
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BD96802_BUCK2_UVD_STAT,
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BD96802_BUCK2_TW_CH_STAT,
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};
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#endif
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