Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
60 lines
2.4 KiB
Plaintext
60 lines
2.4 KiB
Plaintext
What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Enable/disable tracing on this specific trace macrocell.
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Enabling the trace macrocell implies it has been configured
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properly and a sink has been identified for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Provides access to the HW event enable register, used in
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conjunction with HW event bank select register.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Gives access to the HW event block select register
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(STMHEBSR) in order to configure up to 256 channels. Used in
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conjunction with "hwevent_enable" register as described above.
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What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Provides access to the stimulus port enable register
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(STMSPER). Used in conjunction with "port_select" described
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below.
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What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used to determine which bank of stimulus port bit in
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register STMSPER (see above) apply to.
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What: /sys/bus/coresight/devices/<memory_map>.stm/status
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) List various control and status registers. The specific
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layout and content is driver specific.
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What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Holds the trace ID that will appear in the trace stream
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coming from this trace entity.
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What: /sys/bus/coresight/devices/<memory_map>.stm/label
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Date: Aug 2025
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KernelVersion 6.18
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Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
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Description: (Read) Show hardware context information of device.
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