Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
68 lines
1.9 KiB
YAML
68 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom GISB bus Arbiter controller
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- brcm,bcm7445-gisb-arb # for other 28nm chips
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- const: brcm,gisb-arb
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- items:
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- enum:
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- brcm,bcm74165-gisb-arb # for V7 new style 16nm chips
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- brcm,bcm7278-gisb-arb # for V7 28nm chips
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- brcm,bcm7435-gisb-arb # for newer 40nm chips
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- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
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- brcm,bcm7038-gisb-arb # for 130nm chips
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- brcm,gisb-arb # fallback compatible
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reg:
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maxItems: 1
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interrupts:
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minItems: 2
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items:
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- description: timeout interrupt line
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- description: target abort interrupt line
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- description: breakpoint interrupt line
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brcm,gisb-arb-master-mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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32-bits wide bitmask used to specify which GISB masters are valid at the
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system level
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brcm,gisb-arb-master-names:
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$ref: /schemas/types.yaml#/definitions/string-array
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description: >
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String list of the literal name of the GISB masters. Should match the
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number of bits set in brcm,gisb-master-mask and the order in which they
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appear from MSB to LSB.
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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gisb-arb@f0400000 {
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compatible = "brcm,gisb-arb";
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reg = <0xf0400000 0x800>;
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interrupts = <0>, <2>;
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interrupt-parent = <&sun_l2_intc>;
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brcm,gisb-arb-master-mask = <0x7>;
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brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
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};
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