Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
48 lines
1016 B
YAML
48 lines
1016 B
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIESYS clock and reset controller
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description:
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The MediaTek PCIESYS controller provides various clocks to the system.
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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properties:
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compatible:
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oneOf:
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- items:
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- const: mediatek,mt7622-pciesys
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- const: syscon
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- const: mediatek,mt7629-pciesys
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
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"#reset-cells":
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const: 1
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required:
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@1a100800 {
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compatible = "mediatek,mt7622-pciesys", "syscon";
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reg = <0x1a100800 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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