Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
146 lines
4.0 KiB
YAML
146 lines
4.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Anusha Rao <quic_anusha@quicinc.com>
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description: |
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Qualcomm networking sub system clock control module provides the clocks,
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resets on IPQ9574 and IPQ5424
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See also:
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include/dt-bindings/clock/qcom,ipq5424-nsscc.h
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include/dt-bindings/clock/qcom,ipq9574-nsscc.h
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include/dt-bindings/reset/qcom,ipq5424-nsscc.h
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include/dt-bindings/reset/qcom,ipq9574-nsscc.h
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properties:
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compatible:
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enum:
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- qcom,ipq5424-nsscc
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- qcom,ipq9574-nsscc
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clocks:
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items:
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- description: Board XO source
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- description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
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can vary for different IPQ SoCs. For example, it is 1200 MHz on the
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IPQ9574 and 300 MHz on the IPQ5424.
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- description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
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rate can vary for different IPQ SoCs. For example, it is 353 MHz
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on the IPQ9574 and 375 MHz on the IPQ5424.
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- description: GCC GPLL0 OUT AUX clock source
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- description: Uniphy0 NSS Rx clock source
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- description: Uniphy0 NSS Tx clock source
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- description: Uniphy1 NSS Rx clock source
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- description: Uniphy1 NSS Tx clock source
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- description: Uniphy2 NSS Rx clock source
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- description: Uniphy2 NSS Tx clock source
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- description: GCC NSSCC clock source
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'#interconnect-cells':
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const: 1
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clock-names:
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items:
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- const: xo
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- enum:
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- nss_1200
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- nss
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- enum:
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- ppe_353
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- ppe
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- const: gpll0_out
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- const: uniphy0_rx
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- const: uniphy0_tx
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- const: uniphy1_rx
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- const: uniphy1_tx
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- const: uniphy2_rx
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- const: uniphy2_tx
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- const: bus
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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properties:
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compatible:
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const: qcom,ipq9574-nsscc
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then:
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properties:
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clock-names:
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items:
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- const: xo
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- const: nss_1200
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- const: ppe_353
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- const: gpll0_out
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- const: uniphy0_rx
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- const: uniphy0_tx
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- const: uniphy1_rx
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- const: uniphy1_tx
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- const: uniphy2_rx
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- const: uniphy2_tx
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- const: bus
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else:
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properties:
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clock-names:
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items:
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- const: xo
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- const: nss
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- const: ppe
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- const: gpll0_out
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- const: uniphy0_rx
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- const: uniphy0_tx
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- const: uniphy1_rx
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- const: uniphy1_tx
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- const: uniphy2_rx
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- const: uniphy2_tx
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- const: bus
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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clock-controller@39b00000 {
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compatible = "qcom,ipq9574-nsscc";
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reg = <0x39b00000 0x80000>;
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clocks = <&xo_board_clk>,
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<&cmn_pll NSS_1200MHZ_CLK>,
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<&cmn_pll PPE_353MHZ_CLK>,
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<&gcc GPLL0_OUT_AUX>,
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<&uniphy 0>,
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<&uniphy 1>,
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<&uniphy 2>,
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<&uniphy 3>,
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<&uniphy 4>,
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<&uniphy 5>,
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<&gcc GCC_NSSCC_CLK>;
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clock-names = "xo",
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"nss_1200",
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"ppe_353",
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"gpll0_out",
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"uniphy0_rx",
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"uniphy0_tx",
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"uniphy1_rx",
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"uniphy1_tx",
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"uniphy2_rx",
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"uniphy2_tx",
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"bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#interconnect-cells = <1>;
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};
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...
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