Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
60 lines
1.5 KiB
YAML
60 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <quic_ajipan@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM4450
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See also: include/dt-bindings/clock/qcom,sm4450-dispcc.h
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properties:
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compatible:
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const: qcom,sm4450-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Display AHB clock source from GCC
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- description: sleep clock source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,sm4450-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy_pll_out_byteclk>,
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<&dsi0_phy_pll_out_dsiclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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