Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
49 lines
1.1 KiB
YAML
49 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed BMC SoC SDRAM EDAC controller
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maintainers:
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- Stefan Schaeckeler <sschaeck@cisco.com>
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description: >
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The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
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correction check).
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The memory controller supports SECDED (single bit error correction, double bit
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error detection) and single bit error auto scrubbing by reserving 8 bits for
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every 64 bit word (effectively reducing available memory to 8/9).
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Note, the bootloader must configure ECC mode in the memory controller.
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properties:
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compatible:
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enum:
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- aspeed,ast2400-sdram-edac
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- aspeed,ast2500-sdram-edac
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- aspeed,ast2600-sdram-edac
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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sdram@1e6e0000 {
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compatible = "aspeed,ast2500-sdram-edac";
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reg = <0x1e6e0000 0x174>;
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interrupts = <0>;
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};
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