Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
60 lines
1.3 KiB
YAML
60 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fpga/lattice,ice40-fpga-mgr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lattice iCE40 FPGA Manager
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maintainers:
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- Joel Holdsworth <joel@airwebreathe.org.uk>
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properties:
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compatible:
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const: lattice,ice40-fpga-mgr
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reg:
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maxItems: 1
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spi-max-frequency:
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minimum: 1000000
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maximum: 25000000
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cdone-gpios:
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maxItems: 1
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description: GPIO input connected to CDONE pin
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reset-gpios:
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maxItems: 1
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description:
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Active-low GPIO output connected to CRESET_B pin. Note that unless the
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GPIO is held low during startup, the FPGA will enter Master SPI mode and
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drive SCK with a clock signal potentially jamming other devices on the bus
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until the firmware is loaded.
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required:
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- compatible
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- reg
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- spi-max-frequency
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- cdone-gpios
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- reset-gpios
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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fpga@0 {
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compatible = "lattice,ice40-fpga-mgr";
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reg = <0>;
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spi-max-frequency = <1000000>;
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cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
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};
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};
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