Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
51 lines
1.2 KiB
Plaintext
51 lines
1.2 KiB
Plaintext
NXP LPC32xx SoC NAND MLC controller
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Required properties:
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- compatible: "nxp,lpc3220-mlc"
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- reg: Address and size of the controller
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- interrupts: The NAND interrupt specification
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- gpios: GPIO specification for NAND write protect
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The following required properties are very controller specific. See the LPC32xx
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User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
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Hz, to make them independent of actual clock speed and to provide for good
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accuracy:)
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- nxp,tcea_delay: TCEA_DELAY
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- nxp,busy_delay: BUSY_DELAY
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- nxp,nand_ta: NAND_TA
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- nxp,rd_high: RD_HIGH
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- nxp,rd_low: RD_LOW
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- nxp,wr_high: WR_HIGH
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- nxp,wr_low: WR_LOW
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Optional subnodes:
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- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
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Example:
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mlc: flash@200a8000 {
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compatible = "nxp,lpc3220-mlc";
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reg = <0x200A8000 0x11000>;
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interrupts = <11 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nxp,tcea-delay = <333333333>;
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nxp,busy-delay = <10000000>;
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nxp,nand-ta = <18181818>;
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nxp,rd-high = <31250000>;
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nxp,rd-low = <45454545>;
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nxp,wr-high = <40000000>;
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nxp,wr-low = <83333333>;
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gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
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mtd0@00000000 {
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label = "boot";
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reg = <0x00000000 0x00064000>;
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read-only;
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};
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...
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};
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