Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
67 lines
1.7 KiB
YAML
67 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CTU CAN FD Open-source IP Core
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description: |
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Open-source CAN FD IP core developed at the Czech Technical University in Prague
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The core sources and documentation on project page
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[1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
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[2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf
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Integration in Xilinx Zynq SoC based system together with
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OpenCores SJA1000 compatible controllers
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[3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
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Martin Jerabek dimploma thesis with integration and testing
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framework description
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[4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf
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maintainers:
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- Pavel Pisa <pisa@cmp.felk.cvut.cz>
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- Ondrej Ille <ondrej.ille@gmail.com>
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- Martin Jerabek <martin.jerabek01@gmail.com>
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allOf:
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- $ref: can-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- const: ctu,ctucanfd-2
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- const: ctu,ctucanfd
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- const: ctu,ctucanfd
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description: |
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phandle of reference clock (100 MHz is appropriate
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for FPGA implementation on Zynq-7000 system).
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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ctu_can_fd_0: can@43c30000 {
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compatible = "ctu,ctucanfd";
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interrupts = <0 30 4>;
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clocks = <&clkc 15>;
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reg = <0x43c30000 0x10000>;
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};
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