Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
100 lines
2.6 KiB
Plaintext
100 lines
2.6 KiB
Plaintext
* PIP Ethernet nexus.
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The PIP Ethernet nexus can control several data packet input/output
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devices. The devices have a two level grouping scheme. There may be
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several interfaces, and each interface may have several ports. These
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ports might be an individual Ethernet PHY.
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Properties for the PIP nexus:
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- compatible: "cavium,octeon-3860-pip"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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- reg: The base address of the PIP's register bank.
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- #address-cells: Must be <1>.
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- #size-cells: Must be <0>.
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Properties for PIP interfaces which is a child the PIP nexus:
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- compatible: "cavium,octeon-3860-pip-interface"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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- reg: The interface number.
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- #address-cells: Must be <1>.
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- #size-cells: Must be <0>.
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Properties for PIP port which is a child the PIP interface:
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- compatible: "cavium,octeon-3860-pip-port"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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- reg: The port number within the interface group.
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- phy-handle: Optional, see ethernet.txt file in the same directory.
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- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
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Value range is 1-31, and mapping to the actual delay varies depending on HW.
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- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
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Value range is 1-31, and mapping to the actual delay varies depending on HW.
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Example:
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pip@11800a0000000 {
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compatible = "cavium,octeon-3860-pip";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11800 0xa0000000 0x0 0x2000>;
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interface@0 {
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compatible = "cavium,octeon-3860-pip-interface";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>; /* interface */
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ethernet@0 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x0>; /* Port */
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local-mac-address = [ 00 0f b7 10 63 60 ];
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phy-handle = <&phy2>;
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};
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ethernet@1 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x1>; /* Port */
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local-mac-address = [ 00 0f b7 10 63 61 ];
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phy-handle = <&phy3>;
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};
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ethernet@2 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x2>; /* Port */
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local-mac-address = [ 00 0f b7 10 63 62 ];
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phy-handle = <&phy4>;
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};
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ethernet@3 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x3>; /* Port */
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local-mac-address = [ 00 0f b7 10 63 63 ];
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phy-handle = <&phy5>;
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};
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};
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interface@1 {
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compatible = "cavium,octeon-3860-pip-interface";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>; /* interface */
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ethernet@0 {
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compatible = "cavium,octeon-3860-pip-port";
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reg = <0x0>; /* Port */
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local-mac-address = [ 00 0f b7 10 63 64 ];
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phy-handle = <&phy6>;
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};
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};
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};
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