Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
131 lines
3.4 KiB
YAML
131 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller
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maintainers:
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- Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
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- Ionut Vicovan <ionut.vicovan@nxp.com>
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description:
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This PCIe controller is based on the Synopsys DesignWare PCIe IP.
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The S32G SoC family has two PCIe controllers, which can be configured as
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either Root Complex or Endpoint.
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properties:
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compatible:
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oneOf:
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- enum:
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- nxp,s32g2-pcie
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- items:
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- const: nxp,s32g3-pcie
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- const: nxp,s32g2-pcie
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reg:
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maxItems: 6
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: dma
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- const: ctrl
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- const: config
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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items:
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- const: msi
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- const: dma
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minItems: 1
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pcie@0:
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description:
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Describe the S32G Root Port.
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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phys:
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maxItems: 1
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required:
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- reg
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- phys
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- ranges
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- pcie@0
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@40400000 {
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compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";
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reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
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<0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
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<0x00 0x40460000 0x0 0x00001000>, /* atu registers */
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<0x00 0x40470000 0x0 0x00001000>, /* dma registers */
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<0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
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<0x5f 0xffffe000 0x0 0x00002000>; /* config space */
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reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config";
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dma-coherent;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges =
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<0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
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<0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,
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<0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;
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bus-range = <0x0 0xff>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi", "dma";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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device_type = "pci";
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phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
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};
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};
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};
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