Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
74 lines
1.9 KiB
YAML
74 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32MP25 PCIe Endpoint
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maintainers:
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- Christian Bruel <christian.bruel@foss.st.com>
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description:
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PCIe endpoint controller based on the Synopsys DesignWare PCIe core.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/st,stm32-pcie-common.yaml#
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properties:
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compatible:
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const: st,stm32mp25-pcie-ep
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: Data Bus Interface (DBI) shadow registers.
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- description: Internal Address Translation Unit (iATU) registers.
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- description: PCIe configuration registers.
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: addr_space
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reset-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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phys:
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maxItems: 1
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required:
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- phys
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/st,stm32mp25-rcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/st,stm32mp25-rcc.h>
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pcie-ep@48400000 {
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compatible = "st,stm32mp25-pcie-ep";
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reg = <0x48400000 0x400000>,
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<0x48500000 0x100000>,
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<0x48700000 0x80000>,
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<0x10000000 0x10000000>;
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reg-names = "dbi", "dbi2", "atu", "addr_space";
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clocks = <&rcc CK_BUS_PCIE>;
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phys = <&combophy PHY_TYPE_PCIE>;
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resets = <&rcc PCIE_R>;
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pinctrl-names = "default", "init";
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pinctrl-0 = <&pcie_pins_a>;
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pinctrl-1 = <&pcie_init_pins_a>;
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reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
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access-controllers = <&rifsc 68>;
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power-domains = <&CLUSTER_PD>;
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};
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