Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
74 lines
1.4 KiB
YAML
74 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip MIPI DPHY with additional LVDS/TTL modes
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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"#phy-cells":
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const: 0
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compatible:
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enum:
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- rockchip,px30-dsi-dphy
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- rockchip,rk3128-dsi-dphy
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- rockchip,rk3368-dsi-dphy
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- rockchip,rk3506-dsi-dphy
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- rockchip,rk3568-dsi-dphy
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- rockchip,rv1126-dsi-dphy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: PLL reference clock
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- description: Module clock
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clock-names:
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items:
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- const: ref
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- const: pclk
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power-domains:
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maxItems: 1
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description: phandle to the associated power domain
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resets:
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items:
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- description: exclusive PHY reset line
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reset-names:
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items:
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- const: apb
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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dsi_dphy: phy@ff2e0000 {
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compatible = "rockchip,px30-dsi-dphy";
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reg = <0xff2e0000 0x10000>;
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clocks = <&pmucru 13>, <&cru 12>;
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clock-names = "ref", "pclk";
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resets = <&cru 12>;
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reset-names = "apb";
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#phy-cells = <0>;
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};
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...
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