Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
125 lines
3.2 KiB
YAML
125 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 37xx SoC pin and gpio controller
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maintainers:
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- Gregory CLEMENT <gregory.clement@bootlin.com>
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- Marek Behún <kabel@kernel.org>
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- Miquel Raynal <miquel.raynal@bootlin.com>
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description: >
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Each Armada 37xx SoC come with two pin and gpio controller one for the south
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bridge and the other for the north bridge.
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Inside this set of register the gpio latch allows exposing some configuration
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of the SoC and especially the clock frequency of the xtal. Hence, this node is
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a represent as syscon allowing sharing the register between multiple hardware
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block.
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properties:
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compatible:
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items:
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- enum:
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- marvell,armada3710-sb-pinctrl
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- marvell,armada3710-nb-pinctrl
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- const: syscon
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- const: simple-mfd
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reg:
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items:
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- description: pinctrl and GPIO controller registers
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- description: interrupt controller registers
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gpio:
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description: GPIO controller subnode
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type: object
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additionalProperties: false
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properties:
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'#gpio-cells':
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const: 2
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gpio-controller: true
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gpio-ranges:
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description: Range of pins managed by the GPIO controller
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'#interrupt-cells':
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const: 2
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interrupt-controller: true
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interrupts:
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description: List of interrupt specifiers for the GPIO controller
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required:
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- '#gpio-cells'
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- gpio-ranges
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- gpio-controller
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- '#interrupt-cells'
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- interrupt-controller
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- interrupts
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xtal-clk:
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type: object
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additionalProperties: false
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properties:
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compatible:
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const: marvell,armada-3700-xtal-clock
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'#clock-cells':
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const: 0
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clock-output-names: true
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patternProperties:
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'-pins$':
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$ref: pinmux-node.yaml#
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additionalProperties: false
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properties:
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groups:
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enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
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pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
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ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
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spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
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usb2_drvvbus1, usb32_drvvbus0 ]
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function:
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enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
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pcie, pmic, ptp, pwm, sdio, smi, spi, uart ]
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl_sb: pinctrl@18800 {
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compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpio {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 29>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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