Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
50 lines
1.2 KiB
YAML
50 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lantiq XWAY SoC RCU reset controller
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maintainers:
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- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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description: |
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This binding describes a reset-controller found on the RCU module on Lantiq
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XWAY SoCs. This node has to be a sub node of the Lantiq RCU block.
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properties:
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compatible:
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enum:
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- lantiq,danube-reset
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- lantiq,xrx200-reset
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reg:
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description: |
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Defines the following sets of registers in the parent syscon device
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Offset of the reset set register
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Offset of the reset status register
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maxItems: 2
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'#reset-cells':
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description: |
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The first cell takes the reset set bit and the second cell takes the
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status bit.
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const: 2
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required:
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- compatible
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- reg
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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// On the xRX200 SoCs:
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reset0: reset-controller@10 {
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compatible = "lantiq,xrx200-reset";
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reg = <0x10 0x04>, <0x14 0x04>;
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#reset-cells = <2>;
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};
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