Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/alpha/kernel/es1888.c
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*
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* Init the built-in ES1888 sound chip (SB16 compatible)
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*/
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#include <linux/init.h>
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#include <asm/io.h>
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#include "proto.h"
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void __init
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es1888_init(void)
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{
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/* Sequence of IO reads to init the audio controller */
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inb(0x0229);
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inb(0x0229);
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inb(0x0229);
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inb(0x022b);
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inb(0x0229);
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inb(0x022b);
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inb(0x0229);
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inb(0x0229);
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inb(0x022b);
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inb(0x0229);
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inb(0x0220); /* This sets the base address to 0x220 */
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/* Sequence to set DMA channels */
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outb(0x01, 0x0226); /* reset */
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inb(0x0226); /* pause */
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outb(0x00, 0x0226); /* release reset */
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while (!(inb(0x022e) & 0x80)) /* wait for bit 7 to assert*/
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continue;
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inb(0x022a); /* pause */
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outb(0xc6, 0x022c); /* enable extended mode */
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inb(0x022a); /* pause, also forces the write */
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while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
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continue;
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outb(0xb1, 0x022c); /* setup for write to Interrupt CR */
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while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
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continue;
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outb(0x14, 0x022c); /* set IRQ 5 */
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while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
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continue;
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outb(0xb2, 0x022c); /* setup for write to DMA CR */
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while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
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continue;
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outb(0x18, 0x022c); /* set DMA channel 1 */
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inb(0x022c); /* force the write */
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}
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