Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
49 lines
820 B
Devicetree
49 lines
820 B
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HiSilicon Ltd. HiP01 SoC
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*
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* Copyright (C) 2014 HiSilicon Ltd.
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* Copyright (C) 2014 Huawei Ltd.
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*
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* Author: Wang Long <long.wanglong@huawei.com>
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*/
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/dts-v1/;
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/* First 8KB reserved for secondary core boot */
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/memreserve/ 0x80000000 0x00002000;
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#include "hip01.dtsi"
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/ {
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model = "Hisilicon HIP01 Development Board";
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compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "hisilicon,hip01-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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