Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
40 lines
688 B
Devicetree
40 lines
688 B
Devicetree
// SPDX-License-Identifier: GPL-2.0
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/*
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* Marvell RD88F6181 A Board descrition
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*
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file contains the definitions for the board with the A0 or
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* higher stepping of the SoC. The ethernet switch does not have a
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* "wan" port.
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*/
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/dts-v1/;
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#include "kirkwood-rd88f6281.dtsi"
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/ {
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model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
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compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
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};
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&mdio {
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status = "okay";
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ethphy1: ethernet-phy@11 {
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reg = <11>;
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};
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};
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&switch {
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reg = <10>;
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};
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ð1 {
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status = "okay";
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ethernet1-port@0 {
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phy-handle = <ðphy1>;
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};
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};
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