Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
45 lines
879 B
Devicetree
45 lines
879 B
Devicetree
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2020 Nuvoton Technology
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#include "nuvoton-common-npcm7xx.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "nuvoton,npcm750-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk NPCM7XX_CLK_CPU>;
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clock-names = "clk_cpu";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk NPCM7XX_CLK_CPU>;
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clock-names = "clk_cpu";
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reg = <1>;
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next-level-cache = <&l2>;
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};
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};
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soc {
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timer@3fe600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x3fe600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&clk NPCM7XX_CLK_AHB>;
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};
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};
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};
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