Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
128 lines
3.0 KiB
Devicetree
128 lines
3.0 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
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// Copyright 2018 Google, Inc.
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#include "nuvoton-common-npcm7xx.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "nuvoton,npcm750-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk NPCM7XX_CLK_CPU>;
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clock-names = "clk_cpu";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk NPCM7XX_CLK_CPU>;
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clock-names = "clk_cpu";
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reg = <1>;
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next-level-cache = <&l2>;
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};
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};
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soc {
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timer@3fe600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x3fe600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&clk NPCM7XX_CLK_AHB>;
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};
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};
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ahb {
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gmac1: ethernet@f0804000 {
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device_type = "network";
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compatible = "snps,dwmac";
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reg = <0xf0804000 0x2000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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ethernet = <1>;
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clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
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clock-names = "stmmaceth", "clk_gmac";
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pinctrl-names = "default";
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pinctrl-0 = <&rg2_pins
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&rg2mdio_pins>;
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status = "disabled";
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};
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udc0: usb@f0830000 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0830000 0x1000
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0xfffd0000 0x800>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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phys = <&udc0_phy>;
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phy_type = "utmi_wide";
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dr_mode = "peripheral";
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status = "disabled";
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};
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udc1: usb@f0831000 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0831000 0x1000
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0xfffd0800 0x800>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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phys = <&udc0_phy>;
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phy_type = "utmi_wide";
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dr_mode = "peripheral";
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status = "disabled";
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};
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udc2: usb@f0832000 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0832000 0x1000
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0xfffd1000 0x800>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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phys = <&udc0_phy>;
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phy_type = "utmi_wide";
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dr_mode = "peripheral";
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status = "disabled";
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};
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udc3: usb@f0833000 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0833000 0x1000
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0xfffd1800 0x800>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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phys = <&udc0_phy>;
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phy_type = "utmi_wide";
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dr_mode = "peripheral";
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status = "disabled";
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};
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udc4: usb@f0834000 {
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compatible = "nuvoton,npcm750-udc";
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reg = <0xf0834000 0x1000
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0xfffd2000 0x800>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_SU>;
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clock-names = "clk_usb_bridge";
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phys = <&udc0_phy>;
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phy_type = "utmi_wide";
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dr_mode = "peripheral";
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status = "disabled";
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};
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};
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};
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