Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
77 lines
2.4 KiB
Devicetree
77 lines
2.4 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright 2018-2022 TQ-Systems GmbH
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* Author: Markus Niebel <Markus.Niebel@tq-group.com>
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*/
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#include "imx6ull.dtsi"
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#include "imx6ul-tqma6ul-common.dtsi"
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#include "imx6ul-tqma6ulx-common.dtsi"
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/ {
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model = "TQ-Systems TQMa6ULL2 SoM";
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compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
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};
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&usdhc2 {
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fsl,tuning-step = <6>;
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/* Errata ERR010450 Workaround */
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max-frequency = <99000000>;
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assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
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assigned-clock-rates = <0>, <198000000>;
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};
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&iomuxc {
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
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/* rst */
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MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
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/* rst */
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MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
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/* rst */
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MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
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>;
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};
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};
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