Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
80 lines
1.5 KiB
Devicetree
80 lines
1.5 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2019 NXP
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/dts-v1/;
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#include "imx7ulp.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Embedded Artists i.MX7ULP COM";
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compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
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chosen {
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stdout-path = &lpuart4;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x4000000>;
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};
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};
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&lpuart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart4>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usdhc0 {
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
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IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
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IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
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IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
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>;
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};
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};
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