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cubelinux-kernel/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
T
Greg Kroah-Hartman 598cf27219 Linux 6.19.3 
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org
Tested-by: Florian Fainelli <florian.fainelli@broadcom.com>
Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com>
Tested-by: Peter Schneider <pschneider1968@googlemail.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Salvatore Bonaccorso <carnil@debian.org>
Tested-by: Brett A C Sheffield <bacs@librecast.net>
Tested-by: Mark Brown <broonie@kernel.org>
Tested-by: Luna Jernberg <droidbittin@gmail.com>
Tested-by: Ronald Warsow <rwarsow@gmx.de>
Tested-by: Justin M. Forbes <jforbes@fedoraproject.org>
Tested-by: Ron Economos <re@w6rz.net>
Tested-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-02-19 16:33:27 +01:00

764 lines
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Qualcomm MSM8960";
compatible = "qcom,msm8960";
interrupt-parent = <&intc>;
clocks {
cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "cxo_board";
};
pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "pxo_board";
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "sleep_clk";
};
};
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
qcom,no-pc-write;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
cpu@0 {
compatible = "qcom,krait";
reg = <0>;
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
cpu@1 {
compatible = "qcom,krait";
reg = <1>;
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
soc: soc {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
rpm: rpm@108000 {
compatible = "qcom,rpm-msm8960";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack",
"err",
"wakeup";
};
ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
qfprom: efuse@700000 {
compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
tsens_backup: backup-calib@414 {
reg = <0x414 0x10>;
};
};
tlmm: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 152>;
#gpio-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
i2c1_default_state: i2c1-default-state {
i2c1-pins {
pins = "gpio8", "gpio9";
function = "gsbi1";
drive-strength = <8>;
bias-disable;
};
};
i2c1_sleep_state: i2c1-sleep-state {
i2c1-pins {
pins = "gpio8", "gpio9";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
i2c3_default_state: i2c3-default-state {
i2c3-pins {
pins = "gpio16", "gpio17";
function = "gsbi3";
drive-strength = <8>;
bias-disable;
};
};
i2c3_sleep_state: i2c3-sleep-state {
i2c3-pins {
pins = "gpio16", "gpio17";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
i2c8_default_state: i2c8-default-state {
i2c8-pins {
pins = "gpio36", "gpio37";
function = "gsbi8";
drive-strength = <8>;
bias-disable;
};
};
i2c8_sleep_state: i2c8-sleep-state {
i2c8-pins {
pins = "gpio36", "gpio37";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
i2c10_default_state: i2c10-default-state {
i2c10-pins {
pins = "gpio73", "gpio74";
function = "gsbi10";
drive-strength = <8>;
bias-disable;
};
};
i2c10_sleep_state: i2c10-sleep-state {
i2c10-pins {
pins = "gpio73", "gpio74";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
i2c12_default_state: i2c12-default-state {
i2c12-pins {
pins = "gpio44", "gpio45";
function = "gsbi12";
drive-strength = <8>;
bias-disable;
};
};
i2c12_sleep_state: i2c12-sleep-state {
i2c12-pins {
pins = "gpio44", "gpio45";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
sdcc3_default_state: sdcc3-default-state {
clk-pins {
pins = "sdc3_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "sdc3_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "sdc3_data";
drive-strength = <8>;
bias-pull-up;
};
};
sdcc3_sleep_state: sdcc3-sleep-state {
clk-pins {
pins = "sdc3_clk";
drive-strength = <2>;
bias-disable;
};
cmd-pins {
pins = "sdc3_cmd";
drive-strength = <2>;
bias-pull-up;
};
data-pins {
pins = "sdc3_data";
drive-strength = <2>;
bias-pull-up;
};
};
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-msm8960", "syscon";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&cxo_board>,
<&pxo_board>,
<&lcc PLL4>;
clock-names = "cxo",
"pxo",
"pll4";
tsens: thermal-sensor {
compatible = "qcom,msm8960-tsens";
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#qcom,sensors = <5>;
#thermal-sensor-cells = <1>;
};
};
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
timer@200a000 {
compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
"qcom,msm-timer";
reg = <0x0200a000 0x100>;
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clock-frequency = <27000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
#clock-cells = <0>;
};
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
saw0: power-manager@2089000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
saw0_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu1_aux";
#clock-cells = <0>;
};
saw1: power-manager@2099000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
saw1_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL3>,
<&gcc PLL8_VOTE>,
<0>,
<0>,
<0>,
<0>,
<0>;
clock-names = "pxo",
"pll3",
"pll8_vote",
"dsi1pll",
"dsi1pllbyte",
"dsi2pll",
"dsi2pllbyte",
"hdmipll";
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x12180000 0x2000>;
arm,primecell-periphid = <0x00051180>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
no-1-8-v;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
status = "disabled";
};
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x4000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
sdcc1: mmc@12400000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x12400000 0x2000>;
arm,primecell-periphid = <0x00051180>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
status = "disabled";
};
sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
gsbi12: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x12480000 0x100>;
ranges;
cell-index = <12>;
clocks = <&gcc GSBI12_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi12_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
pinctrl-0 = <&i2c12_default_state>;
pinctrl-1 = <&i2c12_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_QUP_CLK>,
<&gcc GSBI12_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
usb1: usb@12500000 {
compatible = "qcom,ci-hdrc";
reg = <0x12500000 0x200>,
<0x12500200 0x200>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
clock-names = "core", "iface";
assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
assigned-clock-rates = <60000000>;
resets = <&gcc USB_HS1_RESET>;
reset-names = "core";
phy_type = "ulpi";
ahb-burst-config = <0>;
phys = <&usb_hs1_phy>;
phy-names = "usb-phy";
#reset-cells = <1>;
status = "disabled";
ulpi {
usb_hs1_phy: phy {
compatible = "qcom,usb-hs-phy-msm8960",
"qcom,usb-hs-phy";
clocks = <&sleep_clk>, <&cxo_board>;
clock-names = "sleep", "ref";
resets = <&usb1 0>;
reset-names = "por";
#phy-cells = <0>;
};
};
};
gsbi1: gsbi@16000000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16000000 0x100>;
ranges;
cell-index = <1>;
clocks = <&gcc GSBI1_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi1_i2c: i2c@16080000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16080000 0x1000>;
pinctrl-0 = <&i2c1_default_state>;
pinctrl-1 = <&i2c1_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>,
<&gcc GSBI1_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gsbi1_spi: spi@16080000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x16080000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
cs-gpios = <&tlmm 8 0>;
clocks = <&gcc GSBI1_QUP_CLK>,
<&gcc GSBI1_H_CLK>;
clock-names = "core",
"iface";
status = "disabled";
};
};
gsbi3: gsbi@16200000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
ranges;
cell-index = <3>;
clocks = <&gcc GSBI3_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi3_i2c: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16280000 0x1000>;
pinctrl-0 = <&i2c3_default_state>;
pinctrl-1 = <&i2c3_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI3_QUP_CLK>,
<&gcc GSBI3_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi5: gsbi@16400000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16400000 0x100>;
ranges;
cell-index = <5>;
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
syscon-tcsr = <&tcsr>;
status = "disabled";
gsbi5_serial: serial@16440000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16440000 0x1000>,
<0x16400000 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>,
<&gcc GSBI5_H_CLK>;
clock-names = "core",
"iface";
status = "disabled";
};
};
gsbi8: gsbi@1a000000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x1a000000 0x100>;
ranges;
cell-index = <8>;
clocks = <&gcc GSBI8_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
syscon-tcsr = <&tcsr>;
status = "disabled";
gsbi8_serial: serial@1a040000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a040000 0x1000>,
<0x1a000000 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI8_UART_CLK>,
<&gcc GSBI8_H_CLK>;
clock-names = "core",
"iface";
status = "disabled";
};
gsbi8_i2c: i2c@1a080000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x1a080000 0x1000>;
pinctrl-0 = <&i2c8_default_state>;
pinctrl-1 = <&i2c8_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI8_QUP_CLK>,
<&gcc GSBI8_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gsbi10: gsbi@1a200000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x1a200000 0x100>;
ranges;
cell-index = <10>;
clocks = <&gcc GSBI10_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi10_i2c: i2c@1a280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
pinctrl-0 = <&i2c10_default_state>;
pinctrl-1 = <&i2c10_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI10_QUP_CLK>,
<&gcc GSBI10_H_CLK>;
clock-names = "core",
"iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-msm8960", "syscon";
reg = <0x1a400000 0x100>;
};
rng@1a500000 {
compatible = "qcom,prng";
reg = <0x1a500000 0x200>;
clocks = <&gcc PRNG_CLK>;
clock-names = "core";
};
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-msm8960";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL4_VOTE>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
clock-names = "pxo",
"pll4_vote",
"mi2s_codec_clk",
"codec_i2s_mic_codec_clk",
"spare_i2s_mic_codec_clk",
"codec_i2s_spkr_codec_clk",
"spare_i2s_spkr_codec_clk",
"pcm_codec_clk";
};
};
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
trips {
cpu_alert0: trip0 {
temperature = <60000>;
hysteresis = <10000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <95000>;
hysteresis = <10000>;
type = "critical";
};
};
};
cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
trips {
cpu_alert1: trip0 {
temperature = <60000>;
hysteresis = <10000>;
type = "passive";
};
cpu_crit1: trip1 {
temperature = <95000>;
hysteresis = <10000>;
type = "critical";
};
};
};
};
/* Temporary fixed regulator */
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
};
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