Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
38 lines
900 B
Devicetree
38 lines
900 B
Devicetree
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
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*/
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#include "stm32f746.dtsi"
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/ {
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soc {
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can3: can@40003400 {
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compatible = "st,stm32f4-bxcan";
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reg = <0x40003400 0x200>;
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interrupts = <104>, <105>, <106>, <107>;
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interrupt-names = "tx", "rx0", "rx1", "sce";
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resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
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st,gcan = <&gcan3>;
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status = "disabled";
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};
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gcan3: gcan@40003600 {
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compatible = "st,stm32f4-gcan", "syscon";
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reg = <0x40003600 0x200>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
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};
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dsi: dsi@40016c00 {
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compatible = "st,stm32-dsi";
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reg = <0x40016c00 0x800>;
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clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
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clock-names = "pclk", "ref";
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resets = <&rcc STM32F7_APB2_RESET(DSI)>;
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reset-names = "apb";
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status = "disabled";
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};
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};
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};
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