Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
95 lines
2.4 KiB
Devicetree
95 lines
2.4 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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/*
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* Keystone 2 Edison SoC specific device tree
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*
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* Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
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*/
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clocks {
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mainpllclk: mainpllclk@2310110 {
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#clock-cells = <0>;
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compatible = "ti,keystone,main-pll-clock";
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clocks = <&refclksys>;
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reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
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reg-names = "control", "multiplier", "post-divider";
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};
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papllclk: papllclk@2620358 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkpass>;
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clock-output-names = "papllclk";
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reg = <0x02620358 4>;
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reg-names = "control";
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};
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ddr3apllclk: ddr3apllclk@2620360 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkddr3a>;
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clock-output-names = "ddr-3a-pll-clk";
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reg = <0x02620360 4>;
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reg-names = "control";
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};
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clkusb1: clkusb1@2350004 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "usb1";
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reg = <0x02350004 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clkhyperlink0: clkhyperlink0@2350030 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "hyperlink-0";
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reg = <0x02350030 0xb00>, <0x02350014 0x400>;
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reg-names = "control", "domain";
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domain-id = <5>;
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};
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clkpcie1: clkpcie1@235006c {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "pcie1";
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reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
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reg-names = "control", "domain";
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domain-id = <18>;
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};
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clkxge: clkxge@23500c8 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "xge";
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reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
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reg-names = "control", "domain";
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domain-id = <29>;
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};
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/*
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* Below are set of fixed, input clocks definitions,
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* for which real frequencies have to be defined in board files.
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* Those clocks can be used as reference clocks for some HW modules
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* (as cpts, for example) by configuring corresponding clock muxes.
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*/
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tsipclka: tsipclka {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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clock-output-names = "tsipclka";
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};
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tsipclkb: tsipclkb {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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clock-output-names = "tsipclkb";
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};
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};
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