Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP2-specific DPLL control functions
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*
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* Copyright (C) 2011 Nokia Corporation
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* Paul Walmsley
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "cm2xxx.h"
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#include "cm-regbits-24xx.h"
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/* Private functions */
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/**
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* _allow_idle - enable DPLL autoidle bits
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* @clk: struct clk * of the DPLL to operate on
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*
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* Enable DPLL automatic idle control. The DPLL will enter low-power
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* stop when its downstream clocks are gated. No return value.
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* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
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* instead. Add some mechanism to optionally enter this mode.
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*/
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static void _allow_idle(struct clk_hw_omap *clk)
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{
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if (!clk || !clk->dpll_data)
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return;
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omap2xxx_cm_set_dpll_auto_low_power_stop();
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}
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/**
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* _deny_idle - prevent DPLL from automatically idling
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* @clk: struct clk * of the DPLL to operate on
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*
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* Disable DPLL automatic idle control. No return value.
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*/
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static void _deny_idle(struct clk_hw_omap *clk)
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{
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if (!clk || !clk->dpll_data)
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return;
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omap2xxx_cm_set_dpll_disable_autoidle();
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}
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/* Public data */
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const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
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.allow_idle = _allow_idle,
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.deny_idle = _deny_idle,
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};
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