Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
31 lines
862 B
C
31 lines
862 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Orion CPU Bridge Registers */
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include "orion5x.h"
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#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
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#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
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#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
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#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
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#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
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#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
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#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
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#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
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#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
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#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
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#endif
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