Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
30 lines
771 B
C
30 lines
771 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Marvell Tauros3 cache controller includes
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on GPL'ed 2.6 kernel sources
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* (c) Marvell International Ltd.
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*/
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#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
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#define __ASM_ARM_HARDWARE_TAUROS3_H
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/*
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* Marvell Tauros3 L2CC is compatible with PL310 r0p0
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* but with PREFETCH_CTRL (r2p0) and an additional event counter.
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* Also, there is AUX2_CTRL for some Marvell specific control.
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*/
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#define TAUROS3_EVENT_CNT2_CFG 0x224
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#define TAUROS3_EVENT_CNT2_VAL 0x228
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#define TAUROS3_INV_ALL 0x780
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#define TAUROS3_CLEAN_ALL 0x784
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#define TAUROS3_AUX2_CTRL 0x820
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/* Registers shifts and masks */
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#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2)
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#endif
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