Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
150 lines
3.0 KiB
Devicetree
150 lines
3.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include "meson-g12.dtsi"
|
|
|
|
/ {
|
|
compatible = "amlogic,g12a";
|
|
|
|
cpus {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
d-cache-line-size = <32>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-sets = <32>;
|
|
i-cache-line-size = <32>;
|
|
i-cache-size = <0x8000>;
|
|
i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
d-cache-line-size = <32>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-sets = <32>;
|
|
i-cache-line-size = <32>;
|
|
i-cache-size = <0x8000>;
|
|
i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
d-cache-line-size = <32>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-sets = <32>;
|
|
i-cache-line-size = <32>;
|
|
i-cache-size = <0x8000>;
|
|
i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
d-cache-line-size = <32>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-sets = <32>;
|
|
i-cache-line-size = <32>;
|
|
i-cache-size = <0x8000>;
|
|
i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
l2: l2-cache0 {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-unified;
|
|
cache-size = <0x80000>; /* L2. 512 KB */
|
|
cache-line-size = <64>;
|
|
cache-sets = <512>;
|
|
};
|
|
};
|
|
|
|
cpu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <731000>;
|
|
clock-latency-ns = <50000>;
|
|
};
|
|
|
|
opp-1200000000 {
|
|
opp-hz = /bits/ 64 <1200000000>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-1398000000 {
|
|
opp-hz = /bits/ 64 <1398000000>;
|
|
opp-microvolt = <761000>;
|
|
};
|
|
|
|
opp-1512000000 {
|
|
opp-hz = /bits/ 64 <1512000000>;
|
|
opp-microvolt = <791000>;
|
|
};
|
|
|
|
opp-1608000000 {
|
|
opp-hz = /bits/ 64 <1608000000>;
|
|
opp-microvolt = <831000>;
|
|
};
|
|
|
|
opp-1704000000 {
|
|
opp-hz = /bits/ 64 <1704000000>;
|
|
opp-microvolt = <861000>;
|
|
};
|
|
|
|
opp-1800000000 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <981000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&cpu_thermal {
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_passive>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <&cpu_hot>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pmu {
|
|
compatible = "amlogic,g12a-ddr-pmu";
|
|
};
|