Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
70 lines
1.5 KiB
Devicetree
70 lines
1.5 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 NXP
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*/
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/dts-v1/;
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#include "imx8ulp-evk.dts"
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/ {
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model = "NXP i.MX8ULP EVK9";
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compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp";
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};
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&btcpu {
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sound-dai = <&sai6>;
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};
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&iomuxc1 {
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pinctrl_sai6: sai6grp {
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fsl,pins = <
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MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43
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MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43
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MX8ULP_PAD_PTE14__I2S6_TXD2 0x43
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MX8ULP_PAD_PTE6__I2S6_RXD0 0x43
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>;
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};
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};
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&pinctrl_enet {
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fsl,pins = <
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MX8ULP_PAD_PTF9__ENET0_MDC 0x43
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MX8ULP_PAD_PTF8__ENET0_MDIO 0x43
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MX8ULP_PAD_PTF5__ENET0_RXER 0x43
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MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43
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MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
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MX8ULP_PAD_PTF0__ENET0_RXD1 0x43
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MX8ULP_PAD_PTF4__ENET0_TXEN 0x43
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MX8ULP_PAD_PTF3__ENET0_TXD0 0x43
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MX8ULP_PAD_PTF2__ENET0_TXD1 0x43
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MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43
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MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
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>;
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};
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&pinctrl_usb1 {
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fsl,pins = <
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MX8ULP_PAD_PTE16__USB0_ID 0x10003
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MX8ULP_PAD_PTE18__USB0_OC 0x10003
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>;
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};
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&pinctrl_usb2 {
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fsl,pins = <
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MX8ULP_PAD_PTD23__USB1_ID 0x10003
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MX8ULP_PAD_PTE20__USB1_OC 0x10003
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>;
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};
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&sai6 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_sai6>;
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pinctrl-1 = <&pinctrl_sai6>;
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assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>;
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assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
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assigned-clock-rates = <12288000>;
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fsl,dataline = <1 0x01 0x04>;
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status = "okay";
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};
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