Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
53 lines
1.0 KiB
Devicetree
53 lines
1.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* Device tree for the CN9130 SoC.
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*/
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#include "armada-ap807-quad.dtsi"
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/ {
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model = "Marvell Armada CN9130 SoC";
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compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
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"marvell,armada-ap807";
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aliases {
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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};
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};
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/*
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* Instantiate the internal CP115
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
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0xe0000000 + ((iface - 1) * 0x1000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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#define CP11X_PCIE2_BASE f2640000
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#include "armada-cp115.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp0_gpio1 {
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status = "okay";
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};
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&cp0_gpio2 {
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status = "okay";
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};
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