Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
84 lines
1.8 KiB
Devicetree
84 lines
1.8 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include "rk3568-hinlink-opc.dtsi"
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/ {
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model = "HINLINK H68K";
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compatible = "hinlink,h68k", "rockchip,rk3568";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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};
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};
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&gmac0 {
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy0>;
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phy-mode = "rgmii-id";
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phy-supply = <&vcc3v3_sys>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus
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&gmac0_rstn>;
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status = "okay";
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};
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&gmac1 {
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy1>;
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phy-mode = "rgmii-id";
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phy-supply = <&vcc3v3_sys>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus
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&gmac1_rstn>;
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status = "okay";
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};
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&mdio0 {
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rgmii_phy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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reset-assert-us = <20000>;
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reset-deassert-us = <100000>;
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reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
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};
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};
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&mdio1 {
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rgmii_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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reset-assert-us = <20000>;
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reset-deassert-us = <100000>;
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reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
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};
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};
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&pinctrl {
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gmac {
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gmac0_rstn: gmac0-rstn {
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rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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gmac1_rstn: gmac1-rstn {
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rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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