Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
160 lines
3.2 KiB
Devicetree
160 lines
3.2 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for AM62A7 SoC family in Quad core configuration
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*
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* TRM: https://www.ti.com/lit/zip/spruj16
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*
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* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am62a.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&a53_opp_table>;
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clocks = <&k3_clks 135 0>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&a53_opp_table>;
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clocks = <&k3_clks 136 0>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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reg = <0x002>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&a53_opp_table>;
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clocks = <&k3_clks 137 0>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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reg = <0x003>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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operating-points-v2 = <&a53_opp_table>;
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clocks = <&k3_clks 138 0>;
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#cooling-cells = <2>;
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};
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};
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a53_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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opp-shared;
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syscon = <&opp_efuse_table>;
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-supported-hw = <0x01 0x0007>;
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clock-latency-ns = <6000000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-supported-hw = <0x01 0x0007>;
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clock-latency-ns = <6000000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-supported-hw = <0x01 0x0007>;
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clock-latency-ns = <6000000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-supported-hw = <0x01 0x0007>;
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clock-latency-ns = <6000000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-supported-hw = <0x01 0x0006>;
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clock-latency-ns = <6000000>;
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};
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opp-1250000000 {
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opp-hz = /bits/ 64 <1250000000>;
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opp-supported-hw = <0x01 0x0004>;
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clock-latency-ns = <6000000>;
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opp-suspend;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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};
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