Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
119 lines
4.2 KiB
Devicetree
119 lines
4.2 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only or MIT
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/*
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* Device Tree Source for AM62L SoC Family
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* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
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*
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* Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "k3-pinctrl.h"
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/ {
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model = "Texas Instruments K3 AM62L3 SoC";
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compatible = "ti,am62l3";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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scmi: scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x82004000>;
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shmem = <&scmi_shmem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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bootph-all;
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};
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scmi_pds: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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bootph-all;
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};
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@f0000 {
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compatible = "simple-bus";
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ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */
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<0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
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<0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */
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<0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */
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<0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */
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<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */
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<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */
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<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */
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<0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
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<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */
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<0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */
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<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
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<0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */
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/* Wakeup Domain Range */
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<0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
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<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
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<0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
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<0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
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<0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
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<0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
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#address-cells = <2>;
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#size-cells = <2>;
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cbass_wakeup: bus@a80000 {
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compatible = "simple-bus";
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ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
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<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
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<0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
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<0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
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<0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
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<0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
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#address-cells = <2>;
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#size-cells = <2>;
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};
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};
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};
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/* Now include peripherals for each bus segment */
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#include "k3-am62l-main.dtsi"
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#include "k3-am62l-wakeup.dtsi"
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