Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
75 lines
1.4 KiB
Devicetree
75 lines
1.4 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
|
/*
|
|
* Device Tree Source for AM65 SoC family in Dual core configuration
|
|
*
|
|
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
#include "k3-am65.dtsi"
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu-map {
|
|
cluster0: cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&cpu1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x000>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
i-cache-size = <0x8000>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x001>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
i-cache-size = <0x8000>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
};
|
|
|
|
L2_0: l2-cache0 {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-unified;
|
|
cache-size = <0x80000>;
|
|
cache-line-size = <64>;
|
|
cache-sets = <512>;
|
|
next-level-cache = <&msmc_l3>;
|
|
};
|
|
|
|
msmc_l3: l3-cache0 {
|
|
compatible = "cache";
|
|
cache-level = <3>;
|
|
cache-unified;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
#include "k3-am654-industrial-thermal.dtsi"
|
|
};
|
|
};
|