Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
114 lines
1.9 KiB
Devicetree
114 lines
1.9 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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#include "dt-bindings/clock/bcm3368-clock.h"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm3368";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <150000000>;
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cpu@0 {
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compatible = "brcm,bmips4350";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "brcm,bmips4350";
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device_type = "cpu";
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reg = <1>;
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};
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};
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clocks {
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periph_clk: periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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cpu_intc: interrupt-controller {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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ubus {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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clkctl: clock-controller@fff8c004 {
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compatible = "brcm,bcm3368-clocks";
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reg = <0xfff8c004 0x4>;
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#clock-cells = <1>;
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};
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periph_cntl: syscon@fff8c008 {
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compatible = "syscon";
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reg = <0xfff8c008 0x4>;
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native-endian;
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};
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reboot: syscon-reboot@fff8c008 {
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compatible = "syscon-reboot";
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regmap = <&periph_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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periph_intc: interrupt-controller@fff8c00c {
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compatible = "brcm,bcm6345-l1-intc";
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reg = <0xfff8c00c 0x8>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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uart0: serial@fff8c100 {
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compatible = "brcm,bcm6345-uart";
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reg = <0xfff8c100 0x18>;
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interrupt-parent = <&periph_intc>;
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interrupts = <2>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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uart1: serial@fff8c120 {
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compatible = "brcm,bcm6345-uart";
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reg = <0xfff8c120 0x18>;
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interrupt-parent = <&periph_intc>;
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interrupts = <3>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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