Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
137 lines
2.8 KiB
Devicetree
137 lines
2.8 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/clock/loongson,ls1x-clk.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
xtal: clock {
|
|
compatible = "fixed-clock";
|
|
clock-output-names = "xtal";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
reg = <0>;
|
|
device_type = "cpu";
|
|
clocks = <&clkc LS1X_CLKID_CPU>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
cpu_intc: interrupt-controller {
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <0>;
|
|
};
|
|
|
|
soc: bus@1fd00000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1fd00000 0x130000>;
|
|
|
|
intc0: interrupt-controller@1040 {
|
|
compatible = "loongson,ls1x-intc";
|
|
reg = <0x1040 0x18>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <2>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
intc1: interrupt-controller@1058 {
|
|
compatible = "loongson,ls1x-intc";
|
|
reg = <0x1058 0x18>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <3>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
intc2: interrupt-controller@1070 {
|
|
compatible = "loongson,ls1x-intc";
|
|
reg = <0x1070 0x18>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <4>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
intc3: interrupt-controller@1088 {
|
|
compatible = "loongson,ls1x-intc";
|
|
reg = <0x1088 0x18>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <5>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio0: gpio@10c0 {
|
|
compatible = "loongson,ls1x-gpio";
|
|
reg = <0x10c0 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@10c4 {
|
|
compatible = "loongson,ls1x-gpio";
|
|
reg = <0x10c4 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
};
|
|
|
|
apb: bus@1fe40000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1fe40000 0xc0000>;
|
|
|
|
uart0: serial@0 {
|
|
compatible = "ns16550a";
|
|
reg = <0x0 0x8>;
|
|
clocks = <&clkc LS1X_CLKID_APB>;
|
|
interrupt-parent = <&intc0>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@4000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x4000 0x8>;
|
|
clocks = <&clkc LS1X_CLKID_APB>;
|
|
interrupt-parent = <&intc0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@8000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x8000 0x8>;
|
|
clocks = <&clkc LS1X_CLKID_APB>;
|
|
interrupt-parent = <&intc0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@c000 {
|
|
compatible = "ns16550a";
|
|
reg = <0xc000 0x8>;
|
|
clocks = <&clkc LS1X_CLKID_APB>;
|
|
interrupt-parent = <&intc0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|