Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
119 lines
2.5 KiB
C
119 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
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*
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* Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
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*/
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#ifndef _GPIO_AU1300_H_
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#define _GPIO_AU1300_H_
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1000.h>
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struct gpio;
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struct gpio_chip;
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/* with the current GPIC design, up to 128 GPIOs are possible.
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* The only implementation so far is in the Au1300, which has 75 externally
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* available GPIOs.
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*/
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#define AU1300_GPIO_BASE 0
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#define AU1300_GPIO_NUM 75
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#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
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#define AU1300_GPIC_ADDR \
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(void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
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static inline int au1300_gpio_get_value(unsigned int gpio)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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int bit;
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gpio -= AU1300_GPIO_BASE;
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roff += GPIC_GPIO_BANKOFF(gpio);
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bit = GPIC_GPIO_TO_BIT(gpio);
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return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
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}
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static inline int au1300_gpio_direction_input(unsigned int gpio)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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unsigned long bit;
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gpio -= AU1300_GPIO_BASE;
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roff += GPIC_GPIO_BANKOFF(gpio);
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bit = GPIC_GPIO_TO_BIT(gpio);
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__raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
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wmb();
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return 0;
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}
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static inline int au1300_gpio_set_value(unsigned int gpio, int v)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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unsigned long bit;
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gpio -= AU1300_GPIO_BASE;
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roff += GPIC_GPIO_BANKOFF(gpio);
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bit = GPIC_GPIO_TO_BIT(gpio);
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__raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
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: AU1300_GPIC_PINVALCLR));
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wmb();
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return 0;
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}
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static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
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{
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/* hw switches to output automatically */
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return au1300_gpio_set_value(gpio, v);
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}
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static inline int au1300_gpio_to_irq(unsigned int gpio)
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{
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return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
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}
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static inline int au1300_irq_to_gpio(unsigned int irq)
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{
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return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
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}
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static inline int au1300_gpio_is_valid(unsigned int gpio)
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{
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int ret;
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1300:
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ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
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break;
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default:
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ret = 0;
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}
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return ret;
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}
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/* hardware remembers gpio 0-63 levels on powerup */
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static inline int au1300_gpio_getinitlvl(unsigned int gpio)
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{
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void __iomem *roff = AU1300_GPIC_ADDR;
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unsigned long v;
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if (unlikely(gpio > 63))
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return 0;
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else if (gpio > 31) {
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gpio -= 32;
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roff += 4;
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}
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v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
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return (v >> gpio) & 1;
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}
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#endif /* _GPIO_AU1300_H_ */
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