Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
37 lines
977 B
C
37 lines
977 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Joshua Henderson <joshua.henderson@microchip.com>
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
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*/
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#ifndef _ASM_MACH_PIC32_H
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#define _ASM_MACH_PIC32_H
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#include <linux/io.h>
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/*
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* PIC32 register offsets for SET/CLR/INV where supported.
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*/
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#define PIC32_CLR(_reg) ((_reg) + 0x04)
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#define PIC32_SET(_reg) ((_reg) + 0x08)
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#define PIC32_INV(_reg) ((_reg) + 0x0C)
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/*
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* PIC32 Base Register Offsets
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*/
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#define PIC32_BASE_CONFIG 0x1f800000
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#define PIC32_BASE_OSC 0x1f801200
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#define PIC32_BASE_RESET 0x1f801240
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#define PIC32_BASE_PPS 0x1f801400
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#define PIC32_BASE_UART 0x1f822000
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#define PIC32_BASE_PORT 0x1f860000
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#define PIC32_BASE_DEVCFG2 0x1fc4ff44
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/*
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* Register unlock sequence required for some register access.
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*/
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void pic32_syskey_unlock_debug(const char *fn, const ulong ln);
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#define pic32_syskey_unlock() \
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pic32_syskey_unlock_debug(__func__, __LINE__)
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#endif /* _ASM_MACH_PIC32_H */
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