Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H
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#define _ASM_POWERPC_NOHASH_32_PTE_85xx_H
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#ifdef __KERNEL__
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/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
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* processors
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*
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MMU Assist Register 3:
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32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
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- PRESENT *must* be in the bottom two bits because swap PTEs use
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the top 30 bits.
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*/
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/* Definitions for FSL Book-E Cores */
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#define _PAGE_READ 0x00001 /* H: Read permission (SR) */
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#define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */
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#define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */
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#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
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#define _PAGE_EXEC 0x00010 /* H: SX permission */
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#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
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#define _PAGE_ENDIAN 0x00040 /* H: E bit */
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#define _PAGE_GUARDED 0x00080 /* H: G bit */
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#define _PAGE_COHERENT 0x00100 /* H: M bit */
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#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
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#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
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#define _PAGE_SPECIAL 0x00800 /* S: Special page */
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#define _PMD_USER 0
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#define _PTE_NONE_MASK 0
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#define PTE_WIMGE_SHIFT (6)
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/*
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* We define 2 sets of base prot bits, one for basic pages (ie,
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* cacheable kernel and user pages) and one for non cacheable
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* pages. We always set _PAGE_COHERENT when SMP is enabled or
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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#else
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#define _PAGE_BASE (_PAGE_BASE_NC)
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#endif
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#include <asm/pgtable-masks.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */
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