Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
88 lines
2.0 KiB
ArmAsm
88 lines
2.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the 64-bit prom entry code.
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*/
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/exception-64s.h>
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#else
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#include <asm/exception-64e.h>
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#endif
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#include <asm/ppc_asm.h>
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.section ".text","ax",@progbits
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_GLOBAL(enter_prom)
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mflr r0
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std r0,16(r1)
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stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
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/* Because PROM is running in 32b mode, it clobbers the high order half
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* of all registers that it saves. We therefore save those registers
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* PROM might touch to the stack. (r0, r3-r13 are caller saved)
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*/
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SAVE_GPR(2, r1)
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SAVE_GPR(13, r1)
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SAVE_NVGPRS(r1)
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mfcr r10
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mfmsr r11
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std r10,_CCR(r1)
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std r11,_MSR(r1)
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/* Put PROM address in SRR0 */
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mtsrr0 r4
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/* Setup our trampoline return addr in LR */
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bcl 20,31,$+4
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0: mflr r4
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addi r4,r4,(1f - 0b)
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mtlr r4
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/* Prepare a 32-bit mode big endian MSR
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*/
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#ifdef CONFIG_PPC_BOOK3E_64
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rlwinm r11,r11,0,1,31
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mtsrr1 r11
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rfi
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#else /* CONFIG_PPC_BOOK3E_64 */
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LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_LE)
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andc r11,r11,r12
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mtsrr1 r11
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RFI_TO_KERNEL
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#endif /* CONFIG_PPC_BOOK3E_64 */
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1: /* Return from OF */
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FIXUP_ENDIAN
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/* Just make sure that r1 top 32 bits didn't get
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* corrupt by OF
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*/
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rldicl r1,r1,0,32
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/* Restore the MSR (back to 64 bits) */
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ld r0,_MSR(r1)
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MTMSRD(r0)
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isync
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/* Restore other registers */
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REST_GPR(2, r1)
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REST_GPR(13, r1)
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REST_NVGPRS(r1)
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ld r4,_CCR(r1)
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mtcr r4
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addi r1,r1,SWITCH_FRAME_SIZE
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ld r0,16(r1)
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mtlr r0
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blr
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