Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
59 lines
1.5 KiB
Devicetree
59 lines
1.5 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2025 Microchip Technology Inc */
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/ {
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core_pwm0: pwm@40000000 {
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x40000000 0x0 0xF0>;
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microchip,sync-update-mask = /bits/ 32 <0>;
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#pwm-cells = <3>;
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clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
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status = "disabled";
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};
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i2c2: i2c@40000200 {
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compatible = "microchip,corei2c-rtl-v7";
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reg = <0x0 0x40000200 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
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interrupt-parent = <&plic>;
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interrupts = <122>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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ihc: mailbox {
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compatible = "microchip,sbi-ipc";
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>, <177>;
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interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
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#mbox-cells = <1>;
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status = "disabled";
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};
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mailbox@50000000 {
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compatible = "microchip,miv-ihc-rtl-v2";
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reg = <0x0 0x50000000 0x0 0x1c000>;
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>, <177>;
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interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
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#mbox-cells = <1>;
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microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
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status = "disabled";
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};
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refclk_ccc: clock-cccref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_sw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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