Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
139 lines
2.1 KiB
Devicetree
139 lines
2.1 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2022 Microchip Technology Inc */
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/dts-v1/;
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#include "mpfs.dtsi"
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#include "mpfs-sev-kit-fabric.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip PolarFire-SoC SEV Kit";
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compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
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aliases {
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ethernet0 = &mac1;
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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serial4 = &mmuart4;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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fabricbuf0ddrc: buffer@80000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x80000000 0x0 0x2000000>;
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};
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fabricbuf1ddrnc: buffer@c4000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xc4000000 0x0 0x4000000>;
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};
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fabricbuf2ddrncwcb: buffer@d4000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0xd4000000 0x0 0x4000000>;
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};
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};
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ddrc_cache: memory@1000000000 {
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device_type = "memory";
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reg = <0x10 0x0 0x0 0x76000000>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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status = "okay";
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};
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&mac0 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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phy1: ethernet-phy@9 {
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reg = <9>;
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};
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phy0: ethernet-phy@8 {
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reg = <8>;
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};
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};
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&mac1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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status = "okay";
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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};
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&mmuart1 {
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status = "okay";
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};
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&mmuart2 {
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status = "okay";
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};
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&mmuart3 {
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status = "okay";
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};
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&mmuart4 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&rtc {
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status = "okay";
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};
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&syscontroller {
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status = "okay";
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};
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&usb {
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status = "okay";
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dr_mode = "otg";
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};
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