Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
109 lines
2.8 KiB
Devicetree
109 lines
2.8 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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// Copyright 2025 Tenstorrent AI ULC
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/dts-v1/;
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/ {
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compatible = "tenstorrent,blackhole";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <50000000>;
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cpu@0 {
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compatible = "sifive,x280", "sifive,rocket0", "riscv";
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device_type = "cpu";
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reg = <0>;
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mmu-type = "riscv,sv57";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
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"zifencei", "zfh", "zba", "zbb", "sscofpmf";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@1 {
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compatible = "sifive,x280", "sifive,rocket0", "riscv";
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device_type = "cpu";
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reg = <1>;
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mmu-type = "riscv,sv57";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
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"zifencei", "zfh", "zba", "zbb", "sscofpmf";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@2 {
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compatible = "sifive,x280", "sifive,rocket0", "riscv";
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device_type = "cpu";
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reg = <2>;
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mmu-type = "riscv,sv57";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
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"zifencei", "zfh", "zba", "zbb", "sscofpmf";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@3 {
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compatible = "sifive,x280", "sifive,rocket0", "riscv";
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device_type = "cpu";
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reg = <3>;
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mmu-type = "riscv,sv57";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
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"zifencei", "zfh", "zba", "zbb", "sscofpmf";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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clint0: timer@2000000 {
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compatible = "tenstorrent,blackhole-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
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<&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
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<&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
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<&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
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};
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plic0: interrupt-controller@c000000 {
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compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0";
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reg = <0x0 0x0c000000 0x0 0x04000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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riscv,ndev = <128>;
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};
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};
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};
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