Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
94 lines
2.1 KiB
C
94 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* x86 KFENCE support.
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*
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* Copyright (C) 2020, Google LLC.
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*/
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#ifndef _ASM_X86_KFENCE_H
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#define _ASM_X86_KFENCE_H
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#ifndef MODULE
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#include <linux/bug.h>
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#include <linux/kfence.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/set_memory.h>
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#include <asm/tlbflush.h>
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/* Force 4K pages for __kfence_pool. */
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static inline bool arch_kfence_init_pool(void)
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{
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unsigned long addr;
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for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr);
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addr += PAGE_SIZE) {
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unsigned int level;
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if (!lookup_address(addr, &level))
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return false;
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if (level != PG_LEVEL_4K)
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set_memory_4k(addr, 1);
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}
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return true;
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}
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/* Protect the given page and flush TLB. */
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static inline bool kfence_protect_page(unsigned long addr, bool protect)
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{
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unsigned int level;
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pte_t *pte = lookup_address(addr, &level);
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pteval_t val, new;
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if (WARN_ON(!pte || level != PG_LEVEL_4K))
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return false;
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val = pte_val(*pte);
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/*
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* protect requires making the page not-present. If the PTE is
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* already in the right state, there's nothing to do.
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*/
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if (protect != !!(val & _PAGE_PRESENT))
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return true;
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/*
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* Otherwise, flip the Present bit, taking care to avoid writing an
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* L1TF-vulnerable PTE (not present, without the high address bits
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* set).
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*/
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new = val ^ _PAGE_PRESENT;
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set_pte(pte, __pte(flip_protnone_guard(val, new, PTE_PFN_MASK)));
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/*
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* If the page was protected (non-present) and we're making it
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* present, there is no need to flush the TLB at all.
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*/
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if (!protect)
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return true;
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/*
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* We need to avoid IPIs, as we may get KFENCE allocations or faults
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* with interrupts disabled. Therefore, the below is best-effort, and
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* does not flush TLBs on all CPUs. We can tolerate some inaccuracy;
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* lazy fault handling takes care of faults after the page is PRESENT.
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*/
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/*
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* Flush this CPU's TLB, assuming whoever did the allocation/free is
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* likely to continue running on this CPU.
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*/
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preempt_disable();
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flush_tlb_one_kernel(addr);
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preempt_enable();
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return true;
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}
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#endif /* !MODULE */
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#endif /* _ASM_X86_KFENCE_H */
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