Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
94 lines
3.5 KiB
C
94 lines
3.5 KiB
C
/*
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* Routines to identify additional cpu features that are scattered in
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* cpuid space.
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*/
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#include <linux/cpu.h>
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#include <asm/memtype.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include "cpu.h"
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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u8 bit;
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u32 level;
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u32 sub_leaf;
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};
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/*
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* Please keep the leaf sorted by cpuid_bit.level for faster search.
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* X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
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* levels are different and there is a separate entry for each.
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*/
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static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
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{ X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
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{ X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
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{ X86_FEATURE_MSR_IMM, CPUID_ECX, 5, 0x00000007, 1 },
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{ X86_FEATURE_APX, CPUID_EDX, 21, 0x00000007, 1 },
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{ X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 },
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{ X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 },
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{ X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
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{ X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
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{ X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
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{ X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
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{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
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{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
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{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
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{ X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
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{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
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{ X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 },
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{ X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
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{ X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
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{ X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 },
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{ X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 },
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{ X86_FEATURE_OVERFLOW_RECOV, CPUID_EBX, 0, 0x80000007, 0 },
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{ X86_FEATURE_SUCCOR, CPUID_EBX, 1, 0x80000007, 0 },
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{ X86_FEATURE_SMCA, CPUID_EBX, 3, 0x80000007, 0 },
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{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
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{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
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{ X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 },
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{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
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{ X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 },
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{ X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 },
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{ X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
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{ X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
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{ X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 },
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{ X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 },
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{ X86_FEATURE_TSA_SQ_NO, CPUID_ECX, 1, 0x80000021, 0 },
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{ X86_FEATURE_TSA_L1_NO, CPUID_ECX, 2, 0x80000021, 0 },
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{ X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 },
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{ X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
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{ X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
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{ X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 },
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{ X86_FEATURE_AMD_HTR_CORES, CPUID_EAX, 30, 0x80000026, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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{
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u32 max_level;
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u32 regs[4];
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const struct cpuid_bit *cb;
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for (cb = cpuid_bits; cb->feature; cb++) {
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/* Verify that the level is valid */
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max_level = cpuid_eax(cb->level & 0xffff0000);
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if (max_level < cb->level ||
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max_level > (cb->level | 0xffff))
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continue;
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cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX],
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®s[CPUID_EBX], ®s[CPUID_ECX],
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®s[CPUID_EDX]);
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if (regs[cb->reg] & (1 << cb->bit))
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set_cpu_cap(c, cb->feature);
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}
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}
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