Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* This header file describes this specific Xtensa processor's TIE extensions
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* that extend basic Xtensa core functionality. It is customized to this
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* Xtensa processor configuration.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999-2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_CORE_TIE_H
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#define _XTENSA_CORE_TIE_H
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#define XCHAL_CP_NUM 0 /* number of coprocessors */
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#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
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#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
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#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
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/* Filler info for unassigned coprocessors, to simplify arrays etc: */
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#define XCHAL_NCP_SA_SIZE 0
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#define XCHAL_NCP_SA_ALIGN 1
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#define XCHAL_CP0_SA_SIZE 0
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#define XCHAL_CP0_SA_ALIGN 1
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#define XCHAL_CP1_SA_SIZE 0
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#define XCHAL_CP1_SA_ALIGN 1
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#define XCHAL_CP2_SA_SIZE 0
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#define XCHAL_CP2_SA_ALIGN 1
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#define XCHAL_CP3_SA_SIZE 0
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#define XCHAL_CP3_SA_ALIGN 1
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#define XCHAL_CP4_SA_SIZE 0
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#define XCHAL_CP4_SA_ALIGN 1
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#define XCHAL_CP5_SA_SIZE 0
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#define XCHAL_CP5_SA_ALIGN 1
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#define XCHAL_CP6_SA_SIZE 0
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#define XCHAL_CP6_SA_ALIGN 1
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#define XCHAL_CP7_SA_SIZE 0
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#define XCHAL_CP7_SA_ALIGN 1
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/* Save area for non-coprocessor optional and custom (TIE) state: */
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#define XCHAL_NCP_SA_SIZE 0
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#define XCHAL_NCP_SA_ALIGN 1
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/* Total save area for optional and custom state (NCP + CPn): */
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#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */
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#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */
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#define XCHAL_NCP_SA_NUM 0
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#define XCHAL_NCP_SA_LIST(s)
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#define XCHAL_CP0_SA_NUM 0
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#define XCHAL_CP0_SA_LIST(s)
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#define XCHAL_CP1_SA_NUM 0
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#define XCHAL_CP1_SA_LIST(s)
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#define XCHAL_CP2_SA_NUM 0
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#define XCHAL_CP2_SA_LIST(s)
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#define XCHAL_CP3_SA_NUM 0
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#define XCHAL_CP3_SA_LIST(s)
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#define XCHAL_CP4_SA_NUM 0
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#define XCHAL_CP4_SA_LIST(s)
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#define XCHAL_CP5_SA_NUM 0
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#define XCHAL_CP5_SA_LIST(s)
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#define XCHAL_CP6_SA_NUM 0
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#define XCHAL_CP6_SA_LIST(s)
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#define XCHAL_CP7_SA_NUM 0
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#define XCHAL_CP7_SA_LIST(s)
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/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
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#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
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#endif /*_XTENSA_CORE_TIE_H*/
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